diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2017-06-22 10:25:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-06-22 10:25:03 +0100 |
| commit | db7a99cdc1d0f4d8cbf7c41ce9e570dce04f0a11 (patch) | |
| tree | 47fd7ac1842e033dc163ed63788bc818af0d5a7e /include/exec | |
| parent | 8dfaf23ae1f2273a9730a9b309cc8471269bb524 (diff) | |
| parent | 8da54b2507c1cabf60c2de904cf0383b23239231 (diff) | |
| download | focaccia-qemu-db7a99cdc1d0f4d8cbf7c41ce9e570dce04f0a11.tar.gz focaccia-qemu-db7a99cdc1d0f4d8cbf7c41ce9e570dce04f0a11.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170619' into staging
Queued TCG patches # gpg: Signature made Mon 19 Jun 2017 19:12:06 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170619: target/arm: Exit after clearing aarch64 interrupt mask target/s390x: Exit after changing PSW mask target/alpha: Use tcg_gen_lookup_and_goto_ptr tcg: Increase hit rate of lookup_tb_ptr tcg/arm: Use ldr (literal) for goto_tb tcg/arm: Try pc-relative addresses for movi tcg/arm: Remove limit on code buffer size tcg/arm: Use indirect branch for goto_tb tcg/aarch64: Use ADR in tcg_out_movi translate-all: consolidate tb init in tb_gen_code tcg: allocate TB structs before the corresponding translated code util: add cacheinfo Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/exec')
| -rw-r--r-- | include/exec/exec-all.h | 5 | ||||
| -rw-r--r-- | include/exec/tb-context.h | 3 |
2 files changed, 3 insertions, 5 deletions
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 87ae10bcc9..724ec73dce 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -301,7 +301,7 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, #define CODE_GEN_AVG_BLOCK_SIZE 150 #endif -#if defined(__arm__) || defined(_ARCH_PPC) \ +#if defined(_ARCH_PPC) \ || defined(__x86_64__) || defined(__i386__) \ || defined(__sparc__) || defined(__aarch64__) \ || defined(__s390x__) || defined(__mips__) \ @@ -401,9 +401,6 @@ static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) #elif defined(__aarch64__) void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); #define tb_set_jmp_target1 aarch64_tb_set_jmp_target -#elif defined(__arm__) -void arm_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); -#define tb_set_jmp_target1 arm_tb_set_jmp_target #elif defined(__sparc__) || defined(__mips__) void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); #else diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h index c7f17f26e0..25c2afe753 100644 --- a/include/exec/tb-context.h +++ b/include/exec/tb-context.h @@ -31,8 +31,9 @@ typedef struct TBContext TBContext; struct TBContext { - TranslationBlock *tbs; + TranslationBlock **tbs; struct qht htable; + size_t tbs_size; int nb_tbs; /* any access to the tbs or the page table must use this lock */ QemuMutex tb_lock; |