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| author | Paulo Alcantara <pcacjr@gmail.com> | 2015-06-28 14:58:56 -0300 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2015-07-07 13:12:22 +0300 |
| commit | 920557971b60e53c2f3f22e5d6c620ab1ed411fd (patch) | |
| tree | 5630d4b1c74b28ba22273d5980ecedcbe367fa38 /include/hw/acpi/ich9.h | |
| parent | 71ba2f0af398f616e154137d9fdda25c2da01324 (diff) | |
| download | focaccia-qemu-920557971b60e53c2f3f22e5d6c620ab1ed411fd.tar.gz focaccia-qemu-920557971b60e53c2f3f22e5d6c620ab1ed411fd.zip | |
ich9: add TCO interface emulation
This interface provides some registers within a 32-byte range and can be acessed through PCI-to-LPC bridge interface (PMBASE + 0x60). It's commonly used as a watchdog timer to detect system lockups through SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If NO_REBOOT bit is not set in GCS (General Control and Status register), the system will be resetted upon second timeout if TCO_RLD register wasn't previously written to prevent timeout. This patch adds support to TCO watchdog logic and few other features like mapping NMIs to SMIs (NMI2SMI_EN bit), system intruder detection, etc. are not implemented yet. Signed-off-by: Paulo Alcantara <pcacjr@zytor.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/acpi/ich9.h')
| -rw-r--r-- | include/hw/acpi/ich9.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index ac24bbe9a3..345fd8d92b 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -25,6 +25,7 @@ #include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/acpi_dev_interface.h" +#include "hw/acpi/tco.h" typedef struct ICH9LPCPMRegs { /* @@ -55,10 +56,15 @@ typedef struct ICH9LPCPMRegs { uint8_t disable_s4; uint8_t s4_val; uint8_t smm_enabled; + bool enable_tco; + TCOIORegs tco_regs; } ICH9LPCPMRegs; void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, - bool smm_enabled, qemu_irq sci_irq); + bool smm_enabled, + bool enable_tco, + qemu_irq sci_irq); + void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base); extern const VMStateDescription vmstate_ich9_pm; |