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| author | Ed Tanous <etanous@nvidia.com> | 2025-07-03 07:42:46 -0700 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-07-03 17:36:45 +0200 |
| commit | 92096685a00414a813aa4735db1706e4e5c6917d (patch) | |
| tree | 12c4efc0e31ad62769d318b4324f715bdb78a4a7 /include/hw/arm/aspeed.h | |
| parent | 6888a4a9c8601005a2329fee6487c3c0df1348c0 (diff) | |
| download | focaccia-qemu-92096685a00414a813aa4735db1706e4e5c6917d.tar.gz focaccia-qemu-92096685a00414a813aa4735db1706e4e5c6917d.zip | |
hw/arm/aspeed: Add second SPI chip to Aspeed model
Aspeed2600 has two spi lanes; Add a new struct that can mount the second SPI. Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'include/hw/arm/aspeed.h')
| -rw-r--r-- | include/hw/arm/aspeed.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 973277bea6..6c36455656 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -35,7 +35,9 @@ struct AspeedMachineClass { uint32_t hw_strap2; const char *fmc_model; const char *spi_model; + const char *spi2_model; uint32_t num_cs; + uint32_t num_cs2; uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); uint32_t uart_default; |