diff options
| author | Guenter Roeck <linux@roeck-us.net> | 2020-03-10 14:51:45 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-12 16:27:33 +0000 |
| commit | bfae1772c4377fdaa1b33ca361edf8d70a7ae820 (patch) | |
| tree | f8b362f9eb791d196765d6e4e97e867598fe0df6 /include/hw/arm/fsl-imx25.h | |
| parent | d6f33c557ce9e4a9c5c7285e7aa71b5884241629 (diff) | |
| download | focaccia-qemu-bfae1772c4377fdaa1b33ca361edf8d70a7ae820.tar.gz focaccia-qemu-bfae1772c4377fdaa1b33ca361edf8d70a7ae820.zip | |
hw/arm/fsl-imx25: Wire up eSDHC controllers
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives provided on the command line to available eSDHC controllers. This patch enables booting the imx25-pdk emulation from SD card. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200310215146.19688-2-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: made commit subject consistent with other patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/fsl-imx25.h')
| -rw-r--r-- | include/hw/arm/fsl-imx25.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 1c86bb55fb..4e2d4868cd 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -27,6 +27,7 @@ #include "hw/misc/imx_rngc.h" #include "hw/i2c/imx_i2c.h" #include "hw/gpio/imx_gpio.h" +#include "hw/sd/sdhci.h" #include "exec/memory.h" #include "target/arm/cpu.h" @@ -38,6 +39,7 @@ #define FSL_IMX25_NUM_EPITS 2 #define FSL_IMX25_NUM_I2CS 3 #define FSL_IMX25_NUM_GPIOS 4 +#define FSL_IMX25_NUM_ESDHCS 2 typedef struct FslIMX25State { /*< private >*/ @@ -54,6 +56,7 @@ typedef struct FslIMX25State { IMXRNGCState rngc; IMXI2CState i2c[FSL_IMX25_NUM_I2CS]; IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; + SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS]; MemoryRegion rom[2]; MemoryRegion iram; MemoryRegion iram_alias; @@ -215,6 +218,10 @@ typedef struct FslIMX25State { #define FSL_IMX25_GPIO3_SIZE 0x4000 #define FSL_IMX25_RNGC_ADDR 0x53FB0000 #define FSL_IMX25_RNGC_SIZE 0x4000 +#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000 +#define FSL_IMX25_ESDHC1_SIZE 0x4000 +#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000 +#define FSL_IMX25_ESDHC2_SIZE 0x4000 #define FSL_IMX25_GPIO1_ADDR 0x53FCC000 #define FSL_IMX25_GPIO1_SIZE 0x4000 #define FSL_IMX25_GPIO2_ADDR 0x53FD0000 @@ -250,5 +257,7 @@ typedef struct FslIMX25State { #define FSL_IMX25_GPIO2_IRQ 51 #define FSL_IMX25_GPIO3_IRQ 16 #define FSL_IMX25_GPIO4_IRQ 23 +#define FSL_IMX25_ESDHC1_IRQ 9 +#define FSL_IMX25_ESDHC2_IRQ 8 #endif /* FSL_IMX25_H */ |