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authorArnaud Minier <arnaud.minier@telecom-paris.fr>2024-03-03 15:06:39 +0100
committerPeter Maydell <peter.maydell@linaro.org>2024-03-05 13:22:56 +0000
commit141c29a23bb8eb63c04199a2c3653195ca14f76a (patch)
treee389a06a18761c4c274b3f747fd7fdf02c0827f7 /include/hw/arm/stm32l4x5_soc.h
parent6487653efd54ea16c9fa39f0f7a648f27bc2c548 (diff)
downloadfocaccia-qemu-141c29a23bb8eb63c04199a2c3653195ca14f76a.tar.gz
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hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexers
Instantiate the whole clock tree and using the Clock multiplexers and
the PLLs defined in the previous commits. This allows to statically
define the clock tree and easily follow the clock signal from one end to
another.

Also handle three-phase reset now that we have defined a known base
state for every object.
(Reset handling based on hw/misc/zynq_sclr.c)

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240303140643.81957-5-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/stm32l4x5_soc.h')
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