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authorLuc Michel <luc.michel@amd.com>2025-09-26 09:07:34 +0200
committerPeter Maydell <peter.maydell@linaro.org>2025-10-07 10:35:36 +0100
commit176faad4bf7565966398df0d6e8cd05825dfceea (patch)
tree913c444cfa13f1e44c30c932416c4a9b190f9ec5 /include/hw/arm/xlnx-versal.h
parent060b809271f9d0d6205fe2232d0aead4a37fa0e7 (diff)
downloadfocaccia-qemu-176faad4bf7565966398df0d6e8cd05825dfceea.tar.gz
focaccia-qemu-176faad4bf7565966398df0d6e8cd05825dfceea.zip
hw/arm/xlnx-versal: rtc: refactor creation
Refactor the RTC device creation using the VersalMap structure.

The sysbus IRQ output 0 (APB IRQ) is connected instead of the output 1
(addr error IRQ). This does not change the current behaviour since the
RTC model does not implement those IRQs anyway.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-17-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/xlnx-versal.h')
-rw-r--r--include/hw/arm/xlnx-versal.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index bba96201d3..abdbed1568 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -17,7 +17,6 @@
 #include "hw/cpu/cluster.h"
 #include "hw/or-irq.h"
 #include "hw/intc/arm_gicv3.h"
-#include "hw/rtc/xlnx-zynqmp-rtc.h"
 #include "qom/object.h"
 #include "hw/misc/xlnx-versal-crl.h"
 #include "net/can_emu.h"
@@ -81,7 +80,6 @@ struct Versal {
 
     /* The Platform Management Controller subsystem.  */
     struct {
-        XlnxZynqMPRTC rtc;
         XlnxVersalCFUAPB cfu_apb;
         XlnxVersalCFUFDRO cfu_fdro;
         XlnxVersalCFUSFR cfu_sfr;