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| author | Arnaud Minier <arnaud.minier@telecom-paris.fr> | 2024-03-03 15:06:36 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-05 13:22:55 +0000 |
| commit | d6b55a0fe9920b46d380f50d7da48ff43de21324 (patch) | |
| tree | 5c87fd762ebb17be5eb41aa6c91716667f462f9e /include/hw/arm | |
| parent | f576e0733ccb023cde94acc7897c78a4871a09d0 (diff) | |
| download | focaccia-qemu-d6b55a0fe9920b46d380f50d7da48ff43de21324.tar.gz focaccia-qemu-d6b55a0fe9920b46d380f50d7da48ff43de21324.zip | |
hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeleton
Add the necessary files to add a simple RCC implementation with just reads from and writes to registers. Also instantiate the RCC in the STM32L4x5_SoC. It is needed for accurate emulation of all the SoC clocks and timers. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240303140643.81957-2-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm')
| -rw-r--r-- | include/hw/arm/stm32l4x5_soc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h index 4f314b7a93..0b4f97e240 100644 --- a/include/hw/arm/stm32l4x5_soc.h +++ b/include/hw/arm/stm32l4x5_soc.h @@ -29,6 +29,7 @@ #include "hw/or-irq.h" #include "hw/misc/stm32l4x5_syscfg.h" #include "hw/misc/stm32l4x5_exti.h" +#include "hw/misc/stm32l4x5_rcc.h" #include "qom/object.h" #define TYPE_STM32L4X5_SOC "stm32l4x5-soc" @@ -47,6 +48,7 @@ struct Stm32l4x5SocState { Stm32l4x5ExtiState exti; OrIRQState exti_or_gates[NUM_EXTI_OR_GATES]; Stm32l4x5SyscfgState syscfg; + Stm32l4x5RccState rcc; MemoryRegion sram1; MemoryRegion sram2; |