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| author | KONRAD Frederic <frederic.konrad@adacore.com> | 2018-05-03 17:17:15 +0200 |
|---|---|---|
| committer | Michael Clark <mjc@sifive.com> | 2018-05-09 07:57:46 +1200 |
| commit | 6fad7d1893f6ea926063067af957009bc320406f (patch) | |
| tree | b49b54fd58d26203dbc863cec652cf32bc381225 /include/hw/boards.h | |
| parent | 17b9751e85b9989cc841ed387794d7f1e8aa5e46 (diff) | |
| download | focaccia-qemu-6fad7d1893f6ea926063067af957009bc320406f.tar.gz focaccia-qemu-6fad7d1893f6ea926063067af957009bc320406f.zip | |
riscv: htif: increase the priority of the htif subregion
The htif device is supposed to be mapped over an other subregion. So increase
its priority to one to avoid any conflict.
Here is the output of info mtree:
Before:
(qemu) info mtree
address-space: memory
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
address-space: I/O
0000000000000000-000000000000ffff (prio 0, i/o): io
address-space: cpu-memory-0
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
After:
(qemu) info mtree
address-space: memory
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
address-space: I/O
0000000000000000-000000000000ffff (prio 0, i/o): io
address-space: cpu-memory-0
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Message-Id: <1525360636-18229-3-git-send-email-frederic.konrad@adacore.com>
Diffstat (limited to 'include/hw/boards.h')
0 files changed, 0 insertions, 0 deletions