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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-21 18:17:46 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-21 18:17:46 +0000 |
| commit | a3c1ca56c0a6ec368a7876f2331b037d066b0b27 (patch) | |
| tree | e57c6d80cd8633cd5b52310e26efe9cb5530ecaf /include/hw/char | |
| parent | 694cf209990f7b7a6f6f30b21010bab92c985175 (diff) | |
| download | focaccia-qemu-a3c1ca56c0a6ec368a7876f2331b037d066b0b27.tar.gz focaccia-qemu-a3c1ca56c0a6ec368a7876f2331b037d066b0b27.zip | |
hw/char/pl011: Support all interrupt lines
The PL011 UART has six interrupt lines: * RX (receive data) * TX (transmit data) * RT (receive timeout) * MS (modem status) * E (errors) * combined (logical OR of all the above) So far we have only emulated the combined interrupt line; add support for the others, so that boards that wire them up to different interrupt controller inputs can do so. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/hw/char')
| -rw-r--r-- | include/hw/char/pl011.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index 1b52bfd5c9..dad3cf2912 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -45,7 +45,7 @@ typedef struct PL011State { int read_count; int read_trigger; CharBackend chr; - qemu_irq irq; + qemu_irq irq[6]; const unsigned char *id; } PL011State; |