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| author | Klaus Jensen <k.jensen@samsung.com> | 2022-05-17 13:07:51 +0200 |
|---|---|---|
| committer | Klaus Jensen <k.jensen@samsung.com> | 2022-06-23 23:24:29 +0200 |
| commit | cc9bcee265a22f6e2391eaa76a0dc2b34469b2a7 (patch) | |
| tree | f93d43f12a1d928fd4137156d61092ecb04bd822 /include/hw/core/accel-cpu.h | |
| parent | 58660bfa3694a2d05eacb8dca7c28ffa08917578 (diff) | |
| download | focaccia-qemu-cc9bcee265a22f6e2391eaa76a0dc2b34469b2a7.tar.gz focaccia-qemu-cc9bcee265a22f6e2391eaa76a0dc2b34469b2a7.zip | |
hw/nvme: clean up CC register write logic
The SRIOV series exposed an issued with how CC register writes are handled and how CSTS is set in response to that. Specifically, after applying the SRIOV series, the controller could end up in a state with CC.EN set to '1' but with CSTS.RDY cleared to '0', causing drivers to expect CSTS.RDY to transition to '1' but timing out. Clean this up. Reviewed-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com> Reviewed-by: Lukasz Maniak <lukasz.maniak@linux.intel.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Diffstat (limited to 'include/hw/core/accel-cpu.h')
0 files changed, 0 insertions, 0 deletions