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| author | Bin Meng <bin.meng@windriver.com> | 2022-04-21 08:33:21 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-22 10:35:16 +1000 |
| commit | b6092544fcbe747c005db25c38d8081d281c79ad (patch) | |
| tree | 9eb946406e188919f3603c486117f35e9dfbf10c /include/hw/core/tcg-cpu-ops.h | |
| parent | 1acdb3b013f4c13a9482cccd9765491f8ed8841c (diff) | |
| download | focaccia-qemu-b6092544fcbe747c005db25c38d8081d281c79ad.tar.gz focaccia-qemu-b6092544fcbe747c005db25c38d8081d281c79ad.zip | |
target/riscv: csr: Hook debug CSR read/write
This adds debug CSR read/write support to the RISC-V CSR RW table. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220421003324.1134983-4-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/core/tcg-cpu-ops.h')
0 files changed, 0 insertions, 0 deletions