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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2024-02-15 15:52:06 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2024-03-12 17:56:55 -0400 |
| commit | 3a95f572112ab4c789d66af666644adcdb2b45a6 (patch) | |
| tree | c6de0405e26845c5192350e02ad3d5d6fe890d2f /include/hw/cxl/cxl_component.h | |
| parent | a8516e5c9719cf45fd81d6790bc9ffdcf753376b (diff) | |
| download | focaccia-qemu-3a95f572112ab4c789d66af666644adcdb2b45a6.tar.gz focaccia-qemu-3a95f572112ab4c789d66af666644adcdb2b45a6.zip | |
hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge.
This CXL component isn't allowed to have a RAS capability. Whilst this should be harmless as software is not expected to look here, good to clean it up. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240215155206.2736-1-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/cxl/cxl_component.h')
| -rw-r--r-- | include/hw/cxl/cxl_component.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 0e5d35c263..5012fab6f7 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -25,6 +25,7 @@ enum reg_type { CXL2_TYPE3_DEVICE, CXL2_LOGICAL_DEVICE, CXL2_ROOT_PORT, + CXL2_RC, CXL2_UPSTREAM_PORT, CXL2_DOWNSTREAM_PORT, CXL3_SWITCH_MAILBOX_CCI, |