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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-09-13 14:25:22 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-10-04 18:15:06 -0400 |
| commit | 61c44bcf510f4db51c28d0288e528cfdf0ebabc3 (patch) | |
| tree | 2426a8ce0d8a5f96fe3e6589343344d8c95c902a /include/hw/cxl/cxl_component.h | |
| parent | 87de174ac49acaa37264e38129596c9819e4a2c5 (diff) | |
| download | focaccia-qemu-61c44bcf510f4db51c28d0288e528cfdf0ebabc3.tar.gz focaccia-qemu-61c44bcf510f4db51c28d0288e528cfdf0ebabc3.zip | |
hw/cxl: Fix and use same calculation for HDM decoder block size everywhere
In order to avoid having the size of the per HDM decoder register block repeated in lots of places, create the register definitions for HDM decoder 1 and use the offset between the first registers in HDM decoder 0 and HDM decoder 1 to establish the offset. Calculate in each function as this is more obvious and leads to shorter line lengths than a single #define which would need a long name to be specific enough. Note that the code currently only supports one decoder, so the bugs this fixes don't actually affect anything. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230913132523.29780-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/cxl/cxl_component.h')
| -rw-r--r-- | include/hw/cxl/cxl_component.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index ef9e033919..7c864d2044 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -148,6 +148,8 @@ REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4) FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1) HDM_DECODER_INIT(0); +/* Only used for HDM decoder registers block address increment */ +HDM_DECODER_INIT(1); /* 8.2.5.13 - CXL Extended Security Capability Structure (Root complex only) */ #define EXTSEC_ENTRY_MAX 256 |