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authorJamin Lin <jamin_lin@aspeedtech.com>2022-05-25 10:31:33 +0200
committerCédric Le Goater <clg@kaod.org>2022-05-25 10:31:33 +0200
commit247c00294a4b3cc694f24811eef07e57eb67aa82 (patch)
tree5a02d372efdf5a2712f23fe485945a4d37e66a09 /include/hw/gpio/aspeed_gpio.h
parent17075ef244d4ca52f7f097927c72b0e09f8d8a5c (diff)
downloadfocaccia-qemu-247c00294a4b3cc694f24811eef07e57eb67aa82.tar.gz
focaccia-qemu-247c00294a4b3cc694f24811eef07e57eb67aa82.zip
hw/gpio support GPIO index mode for write operation.
It did not support GPIO index mode for read operation.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-4-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/gpio/aspeed_gpio.h')
-rw-r--r--include/hw/gpio/aspeed_gpio.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h
index 6dee3cd438..41b36524d0 100644
--- a/include/hw/gpio/aspeed_gpio.h
+++ b/include/hw/gpio/aspeed_gpio.h
@@ -50,6 +50,20 @@ enum GPIORegType {
     gpio_reg_input_mask,
 };
 
+/* GPIO index mode */
+enum GPIORegIndexType {
+    gpio_reg_idx_data = 0,
+    gpio_reg_idx_direction,
+    gpio_reg_idx_interrupt,
+    gpio_reg_idx_debounce,
+    gpio_reg_idx_tolerance,
+    gpio_reg_idx_cmd_src,
+    gpio_reg_idx_input_mask,
+    gpio_reg_idx_reserved,
+    gpio_reg_idx_new_w_cmd_src,
+    gpio_reg_idx_new_r_cmd_src,
+};
+
 typedef struct AspeedGPIOReg {
     uint16_t set_idx;
     enum GPIORegType type;