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| author | Shannon Zhao <zhaoshenglong@huawei.com> | 2018-06-08 13:15:32 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-06-08 13:15:32 +0100 |
| commit | 910e204841954b95c051b2ee49ab0f5c735ff93c (patch) | |
| tree | 7c3abb99db87dd61ceed5d338a19aa0c6f297dcc /include/hw/i2c | |
| parent | bac5ba3dc5da706f52c149fa6c0bd1dc96899bec (diff) | |
| download | focaccia-qemu-910e204841954b95c051b2ee49ab0f5c735ff93c.tar.gz focaccia-qemu-910e204841954b95c051b2ee49ab0f5c735ff93c.zip | |
arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR
While we skip the GIC_INTERNAL irqs, we don't change the register offset accordingly. This will overlap the GICR registers value and leave the last GIC_INTERNAL irq's registers out of update. Fix this by skipping the registers banked by GICR. Also for migration compatibility if the migration source (old version qemu) doesn't send gicd_no_migration_shift_bug = 1 to destination, then we shift the data of PPI to get the right data for SPI. Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 Cc: qemu-stable@nongnu.org Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Message-id: 1527816987-16108-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/i2c')
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