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authorMichael S. Tsirkin <mst@redhat.com>2013-08-27 08:37:26 +0300
committerMichael S. Tsirkin <mst@redhat.com>2013-08-27 10:13:41 +0300
commit1466cef32dd5e7ef3c6477e96d85d92302ad02e3 (patch)
treea5c37ae97d4ec34786244b388701b87cf251f174 /include/hw/i386/pc.h
parent9eda7d373e9c691c070eddcbe3467b991f67f6bd (diff)
downloadfocaccia-qemu-1466cef32dd5e7ef3c6477e96d85d92302ad02e3.tar.gz
focaccia-qemu-1466cef32dd5e7ef3c6477e96d85d92302ad02e3.zip
pc: fix regression for 64 bit PCI memory
commit 398489018183d613306ab022653552247d93919f
    pc: limit 64 bit hole to 2G by default
introduced a way for management to control
the window allocated to the 64 bit PCI hole.

This is useful, but existing management tools do not know how to set
this property.  As a result, e.g. specifying a large ivshmem device with
size > 4G is broken by default.  For example this configuration no
longer works:

-device ivshmem,size=4294967296,chardev=cfoo
-chardev socket,path=/tmp/sock,id=cfoo,server,nowait

Fix this by detecting that hole size was not specified
and defaulting to the backwards-compatible value of 1 << 62.

Cc: qemu-stable@nongnu.org
Cc: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/i386/pc.h')
-rw-r--r--include/hw/i386/pc.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index f79d4782c1..475ba9ee2d 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -106,7 +106,16 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
-#define DEFAULT_PCI_HOLE64_SIZE (1ULL << 31)
+#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
+
+static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
+{
+    if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
+        return 1ULL << 62;
+    } else {
+        return pci_hole64_size;
+    }
+}
 
 void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
                         uint64_t pci_hole64_size);