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authorPhil Dennis-Jordan <phil@philjordan.eu>2017-03-15 19:20:27 +1300
committerPaolo Bonzini <pbonzini@redhat.com>2017-05-03 12:29:40 +0200
commit6103451aeb749e92bf7d730429985189c6921c32 (patch)
tree84405a2567192cbff75286eb005af0f0a440d81e /include/hw/i386/pc.h
parent77af8a2b95b79699de650965d5228772743efe84 (diff)
downloadfocaccia-qemu-6103451aeb749e92bf7d730429985189c6921c32.tar.gz
focaccia-qemu-6103451aeb749e92bf7d730429985189c6921c32.zip
hw/i386: Build-time assertion on pc/q35 reset register being identical.
This adds a clarifying comment and build time assert to the FADT reset register field initialisation: the reset register is the same on both machine types.

Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu>
Message-Id: <1489558827-28971-3-git-send-email-phil@philjordan.eu>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'include/hw/i386/pc.h')
-rw-r--r--include/hw/i386/pc.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index f278b3ae89..416aaa56ea 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -303,6 +303,12 @@ typedef struct PCII440FXState PCII440FXState;
 
 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 
+/*
+ * Reset Control Register: PCI-accessible ISA-Compatible Register at address
+ * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
+ */
+#define RCR_IOPORT 0xcf9
+
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state, int *piix_devfn,
                     ISABus **isa_bus, qemu_irq *pic,