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| author | Radim Krčmář <rkrcmar@redhat.com> | 2016-05-12 19:24:26 +0200 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2016-06-14 16:17:08 -0300 |
| commit | 5232d00a041c8f3628b3532ef35d703a1f0dac19 (patch) | |
| tree | b8be8c9cd1ce38409a68e73a36c44de101662392 /include/hw/i386 | |
| parent | d86c145114183f74114a27ecc8e2117a8b5d51aa (diff) | |
| download | focaccia-qemu-5232d00a041c8f3628b3532ef35d703a1f0dac19.tar.gz focaccia-qemu-5232d00a041c8f3628b3532ef35d703a1f0dac19.zip | |
target-i386: Implement CPUID[0xB] (Extended Topology Enumeration)
I looked at a dozen Intel CPU that have this CPUID and all of them always had Core offset as 1 (a wasted bit when hyperthreading is disabled) and Package offset at least 4 (wasted bits at <= 4 cores). QEMU uses more compact IDs and it doesn't make much sense to change it now. I keep the SMT and Core sub-leaves even if there is just one thread/core; it makes the code simpler and there should be no harm. Signed-off-by: Radim Krčmář <rkrcmar@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'include/hw/i386')
| -rw-r--r-- | include/hw/i386/pc.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ca23609cb7..49566c89d4 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -357,7 +357,12 @@ int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); #define PC_COMPAT_2_6 \ - HW_COMPAT_2_6 + HW_COMPAT_2_6 \ + {\ + .driver = TYPE_X86_CPU,\ + .property = "cpuid-0xb",\ + .value = "off",\ + }, #define PC_COMPAT_2_5 \ PC_COMPAT_2_6 \ |