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| author | Peter Xu <peterx@redhat.com> | 2016-07-14 13:56:23 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2016-07-21 20:43:49 +0300 |
| commit | cb135f59b8059c3a372652377ef92fa4a49ad550 (patch) | |
| tree | 244cb6772ba2773c137cc781d96375083f381d89 /include/hw/i386 | |
| parent | 09cd058a2cf77bb7a3b10ff93c1f80ed88bca364 (diff) | |
| download | focaccia-qemu-cb135f59b8059c3a372652377ef92fa4a49ad550.tar.gz focaccia-qemu-cb135f59b8059c3a372652377ef92fa4a49ad550.zip | |
q35: ioapic: add support for emulated IOAPIC IR
This patch translates all IOAPIC interrupts into MSI ones. One pseudo ioapic address space is added to transfer the MSI message. By default, it will be system memory address space. When IR is enabled, it will be IOMMU address space. Currently, only emulated IOAPIC is supported. Idea suggested by Jan Kiszka and Rita Sinha in the following patch: https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.html Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/i386')
| -rw-r--r-- | include/hw/i386/apic-msidef.h | 1 | ||||
| -rw-r--r-- | include/hw/i386/ioapic_internal.h | 1 | ||||
| -rw-r--r-- | include/hw/i386/pc.h | 4 |
3 files changed, 6 insertions, 0 deletions
diff --git a/include/hw/i386/apic-msidef.h b/include/hw/i386/apic-msidef.h index 6e2eb71f2f..8b4d4cca55 100644 --- a/include/hw/i386/apic-msidef.h +++ b/include/hw/i386/apic-msidef.h @@ -25,6 +25,7 @@ #define MSI_ADDR_REDIRECTION_SHIFT 3 #define MSI_ADDR_DEST_ID_SHIFT 12 +#define MSI_ADDR_DEST_IDX_SHIFT 4 #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 #endif /* HW_APIC_MSIDEF_H */ diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index 0542aa1131..5c901ae78f 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -31,6 +31,7 @@ #define IOAPIC_VERSION 0x11 #define IOAPIC_LVT_DEST_SHIFT 56 +#define IOAPIC_LVT_DEST_IDX_SHIFT 48 #define IOAPIC_LVT_MASKED_SHIFT 16 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15 #define IOAPIC_LVT_REMOTE_IRR_SHIFT 14 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index e38c95a4da..9811125492 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -72,6 +72,10 @@ struct PCMachineState { /* NUMA information: */ uint64_t numa_nodes; uint64_t *node_mem; + + /* Address space used by IOAPIC device. All IOAPIC interrupts + * will be translated to MSI messages in the address space. */ + AddressSpace *ioapic_as; }; #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" |