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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2024-12-19 15:46:43 -0500 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2024-12-19 15:46:43 -0500 |
| commit | 9863d46a5a25bfff7d2195ad5e3127ab3bae0a2b (patch) | |
| tree | 6ae93361a5f0191bd3f314b82b98f04aeed1c697 /include/hw/intc/loongarch_extioi_common.h | |
| parent | 3e9793ab01904144c204589811e0e879109a9713 (diff) | |
| parent | 6f6006ad07243543595c7607ffbeee7f45b94b80 (diff) | |
| download | focaccia-qemu-9863d46a5a25bfff7d2195ad5e3127ab3bae0a2b.tar.gz focaccia-qemu-9863d46a5a25bfff7d2195ad5e3127ab3bae0a2b.zip | |
Merge tag 'pull-loongarch-20241219' of https://gitlab.com/bibo-mao/qemu into staging
loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ2PKBQAKCRAfewwSUazn # 0QAZAQCxbLnvzOb9TPORlg5w0n/xFaKCL7dJbJE4WjlM7dhLkAEA5G8JVoP5Ju2B # mcK7wbymyXNX1ocsukL/JM2JavHS+AI= # =JoSk # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Dec 2024 02:23:49 EST # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20241219' of https://gitlab.com/bibo-mao/qemu: hw/intc/loongarch_extioi: Code cleanup about loongarch_extioi hw/intc/loongarch_extioi: Add pre_save interface hw/intc/loongarch_extioi: Inherit from loongarch_extioi_common hw/intc/loongarch_extioi: Add common file loongarch_extioi_common hw/intc/loongarch_extioi: Add unrealize interface hw/intc/loongarch_extioi: Add common realize interface hw/intc/loongarch_extioi: Rename LoongArchExtIOI with LoongArchExtIOICommonState include: Rename LoongArchExtIOI with LoongArchExtIOICommonState include: Move struct LoongArchExtIOI to header file loongarch_extioi_common include: Add loongarch_extioi_common header file hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic hw/intc/loongarch_pch: Add pre_save and post_load interfaces hw/intc/loongarch_pch: Inherit from loongarch_pic_common hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState hw/intc/loongarch_pch: Merge instance_init() into realize() include: Move struct LoongArchPCHPIC to loongarch_pic_common header file include: Add loongarch_pic_common header file Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'include/hw/intc/loongarch_extioi_common.h')
| -rw-r--r-- | include/hw/intc/loongarch_extioi_common.h | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h new file mode 100644 index 0000000000..f6bc778a85 --- /dev/null +++ b/include/hw/intc/loongarch_extioi_common.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch 3A5000 ext interrupt controller definitions + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#ifndef LOONGARCH_EXTIOI_COMMON_H +#define LOONGARCH_EXTIOI_COMMON_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/loongarch/virt.h" + +#define LS3A_INTC_IP 8 +#define EXTIOI_IRQS (256) +#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8) +/* irq from EXTIOI is routed to no more than 4 cpus */ +#define EXTIOI_CPUS (4) +/* map to ipnum per 32 irqs */ +#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32) +#define EXTIOI_IRQS_COREMAP_SIZE 256 +#define EXTIOI_IRQS_NODETYPE_COUNT 16 +#define EXTIOI_IRQS_GROUP_COUNT 8 + +#define APIC_OFFSET 0x400 +#define APIC_BASE (0x1000ULL + APIC_OFFSET) +#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET) +#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET) +#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET) +#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET) +#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET) +#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET) +#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET) +#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET) +#define EXTIOI_ISR_START (0x700 - APIC_OFFSET) +#define EXTIOI_ISR_END (0x720 - APIC_OFFSET) +#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET) +#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET) +#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET) +#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET) +#define EXTIOI_SIZE 0x800 + +#define EXTIOI_VIRT_BASE (0x40000000) +#define EXTIOI_VIRT_SIZE (0x1000) +#define EXTIOI_VIRT_FEATURES (0x0) +#define EXTIOI_HAS_VIRT_EXTENSION (0) +#define EXTIOI_HAS_ENABLE_OPTION (1) +#define EXTIOI_HAS_INT_ENCODE (2) +#define EXTIOI_HAS_CPU_ENCODE (3) +#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \ + | BIT(EXTIOI_HAS_ENABLE_OPTION) \ + | BIT(EXTIOI_HAS_CPU_ENCODE)) +#define EXTIOI_VIRT_CONFIG (0x4) +#define EXTIOI_ENABLE (1) +#define EXTIOI_ENABLE_INT_ENCODE (2) +#define EXTIOI_ENABLE_CPU_ENCODE (3) +#define EXTIOI_VIRT_COREMAP_START (0x40) +#define EXTIOI_VIRT_COREMAP_END (0x240) + +#define TYPE_LOONGARCH_EXTIOI_COMMON "loongarch_extioi_common" +OBJECT_DECLARE_TYPE(LoongArchExtIOICommonState, + LoongArchExtIOICommonClass, LOONGARCH_EXTIOI_COMMON) + +typedef struct ExtIOICore { + uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT]; + DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS); + qemu_irq parent_irq[LS3A_INTC_IP]; +} ExtIOICore; + +struct LoongArchExtIOICommonState { + SysBusDevice parent_obj; + uint32_t num_cpu; + uint32_t features; + uint32_t status; + /* hardware state */ + uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2]; + uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT]; + uint32_t isr[EXTIOI_IRQS / 32]; + uint32_t enable[EXTIOI_IRQS / 32]; + uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4]; + uint32_t coremap[EXTIOI_IRQS / 4]; + uint32_t sw_pending[EXTIOI_IRQS / 32]; + uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE]; + uint8_t sw_coremap[EXTIOI_IRQS]; + qemu_irq irq[EXTIOI_IRQS]; + ExtIOICore *cpu; + MemoryRegion extioi_system_mem; + MemoryRegion virt_extend; +}; + +struct LoongArchExtIOICommonClass { + SysBusDeviceClass parent_class; + + DeviceRealize parent_realize; + int (*pre_save)(void *s); + int (*post_load)(void *s, int version_id); +}; +#endif /* LOONGARCH_EXTIOI_H */ |