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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-09-25 14:02:32 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-09-25 15:13:24 +0100 |
| commit | 48314d831679373edb13712ff4a1abcb1937a0bd (patch) | |
| tree | df459b5c6c9616a3fc7e5746cfd6fd6e66b2d95a /include/hw/intc | |
| parent | 9f4d2a1316fc294da5c0646fa93894d5f5f0c9a0 (diff) | |
| download | focaccia-qemu-48314d831679373edb13712ff4a1abcb1937a0bd.tar.gz focaccia-qemu-48314d831679373edb13712ff4a1abcb1937a0bd.zip | |
hw/intc/arm_gic: Document QEMU interface
The GICv2's QEMU interface (sysbus MMIO regions, IRQs, etc) is now quite complicated with the addition of the virtualization extensions. Add a comment in the header file which documents it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180823103818.31189-1-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/intc')
| -rw-r--r-- | include/hw/intc/arm_gic.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 42bb535fd4..ed703a1720 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -18,6 +18,49 @@ * with this program; if not, see <http://www.gnu.org/licenses/>. */ +/* + * QEMU interface: + * + QOM property "num-cpu": number of CPUs to support + * + QOM property "num-irq": number of IRQs (including both SPIs and PPIs) + * + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC + * + QOM property "has-security-extensions": set true if the GIC should + * implement the security extensions + * + QOM property "has-virtualization-extensions": set true if the GIC should + * implement the virtualization extensions + * + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32) + * [0..P-1] SPIs + * [P..P+31] PPIs for CPU 0 + * [P+32..P+63] PPIs for CPU 1 + * ... + * + sysbus IRQs: (in order; number will vary depending on number of cores) + * - IRQ for CPU 0 + * - IRQ for CPU 1 + * ... + * - FIQ for CPU 0 + * - FIQ for CPU 1 + * ... + * - VIRQ for CPU 0 (exists even if virt extensions not present) + * - VIRQ for CPU 1 (exists even if virt extensions not present) + * ... + * - VFIQ for CPU 0 (exists even if virt extensions not present) + * - VFIQ for CPU 1 (exists even if virt extensions not present) + * ... + * - maintenance IRQ for CPU i/f 0 (only if virt extensions present) + * - maintenance IRQ for CPU i/f 1 (only if virt extensions present) + * + sysbus MMIO regions: (in order; numbers will vary depending on + * whether virtualization extensions are present and on number of cores) + * - distributor registers (GICD*) + * - CPU interface for the accessing core (GICC*) + * - virtual interface control registers (GICH*) (only if virt extns present) + * - virtual CPU interface for the accessing core (GICV*) (only if virt) + * - CPU 0 CPU interface registers + * - CPU 1 CPU interface registers + * ... + * - CPU 0 virtual interface control registers (only if virt extns present) + * - CPU 1 virtual interface control registers (only if virt extns present) + * ... + */ + #ifndef HW_ARM_GIC_H #define HW_ARM_GIC_H |