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authorVijaya Kumar K <Vijaya.Kumar@cavium.com>2017-02-23 17:21:10 +0530
committerPeter Maydell <peter.maydell@linaro.org>2017-02-28 17:10:00 +0000
commit6692aac41119906409dfa634ecbe3ef1634b5e5c (patch)
tree0937053572eb7d05a61f945ecd788a727665e6ff /include/hw/intc
parent3a5eb5b4a929397d8678df9415c14c691c5ba969 (diff)
downloadfocaccia-qemu-6692aac41119906409dfa634ecbe3ef1634b5e5c.tar.gz
focaccia-qemu-6692aac41119906409dfa634ecbe3ef1634b5e5c.zip
hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
To Save and Restore ICC_SRE_EL1 register introduce vmstate
subsection and load only if non-zero.
Also initialize icc_sre_el1 with to 0x7 in pre_load
function.

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1487850673-26455-3-git-send-email-vijay.kilari@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/intc')
-rw-r--r--include/hw/intc/arm_gicv3_common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 4156051d98..bccdfe17c6 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -172,6 +172,7 @@ struct GICv3CPUState {
     uint8_t gicr_ipriorityr[GIC_INTERNAL];
 
     /* CPU interface */
+    uint64_t icc_sre_el1;
     uint64_t icc_ctlr_el1[2];
     uint64_t icc_pmr_el1;
     uint64_t icc_bpr[3];