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authorKane-Chen-AS <kane_chen@aspeedtech.com>2025-08-12 17:39:59 +0800
committerCédric Le Goater <clg@redhat.com>2025-09-29 18:00:20 +0200
commit9f58dd0a8c30a6b84016db30949fe2f86f8bc38b (patch)
tree437b2489af4aa17f4189973da6c9c5926424b4cb /include/hw/misc/aspeed_sbc.h
parent688a3dae7828ca5ee6f45d510eed083420d72d8a (diff)
downloadfocaccia-qemu-9f58dd0a8c30a6b84016db30949fe2f86f8bc38b.tar.gz
focaccia-qemu-9f58dd0a8c30a6b84016db30949fe2f86f8bc38b.zip
hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC
This patch connects the aspeed.otp device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming
flows.

The following OTP commands are supported:
  - READ: reads a 32-bit word from OTP memory into internal registers
  - PROG: programs a 32-bit word value to the specified OTP address

Trace events are added to observe read/program operations and command
handling flow.

Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-3-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'include/hw/misc/aspeed_sbc.h')
-rw-r--r--include/hw/misc/aspeed_sbc.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h
index 405e6782b9..0c2746d392 100644
--- a/include/hw/misc/aspeed_sbc.h
+++ b/include/hw/misc/aspeed_sbc.h
@@ -10,6 +10,7 @@
 #define ASPEED_SBC_H
 
 #include "hw/sysbus.h"
+#include "hw/nvram/aspeed_otp.h"
 
 #define TYPE_ASPEED_SBC "aspeed.sbc"
 #define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
@@ -36,10 +37,14 @@ struct AspeedSBCState {
     MemoryRegion iomem;
 
     uint32_t regs[ASPEED_SBC_NR_REGS];
+
+    AspeedOTPState otp;
 };
 
 struct AspeedSBCClass {
     SysBusDeviceClass parent_class;
+
+    bool has_otp;
 };
 
 #endif /* ASPEED_SBC_H */