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| author | Luc Michel <luc@lmichel.fr> | 2020-10-10 15:57:56 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-27 11:10:44 +0000 |
| commit | 502960ca04c15cc7e24f3e8f9e0d8070bc3d77d7 (patch) | |
| tree | db3f113ffa05bf1b95d691fa67c1d1eebf805dc0 /include/hw/misc/bcm2835_cprman_internals.h | |
| parent | fc9840850ba0eb3e61c81894bff3df12b0534497 (diff) | |
| download | focaccia-qemu-502960ca04c15cc7e24f3e8f9e0d8070bc3d77d7.tar.gz focaccia-qemu-502960ca04c15cc7e24f3e8f9e0d8070bc3d77d7.zip | |
hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
This simple mux sits between the PLL channels and the DSI0E and DSI0P clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel and outputs the selected signal to source number 4 of DSI0E/P clock muxes. It is controlled by the cm_dsi0hsck register. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/misc/bcm2835_cprman_internals.h')
| -rw-r--r-- | include/hw/misc/bcm2835_cprman_internals.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h index 0305448bbc..a6e799075f 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -15,6 +15,7 @@ #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll" #define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel" #define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux" +#define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux" DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL, TYPE_CPRMAN_PLL) @@ -22,6 +23,8 @@ DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL, TYPE_CPRMAN_PLL_CHANNEL) DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX, TYPE_CPRMAN_CLOCK_MUX) +DECLARE_INSTANCE_CHECKER(CprmanDsi0HsckMuxState, CPRMAN_DSI0HSCK_MUX, + TYPE_CPRMAN_DSI0HSCK_MUX) /* Register map */ @@ -223,6 +226,9 @@ REG32(CM_LOCK, 0x114) FIELD(CM_LOCK, FLOCKB, 9, 1) FIELD(CM_LOCK, FLOCKA, 8, 1) +REG32(CM_DSI0HSCK, 0x120) + FIELD(CM_DSI0HSCK, SELPLLD, 0, 1) + /* * This field is common to all registers. Each register write value must match * the CPRMAN_PASSWORD magic value in its 8 MSB. |