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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-02-19 14:45:49 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-08 17:20:02 +0000 |
| commit | 2672a6ca72311bdf97f9e324ab2e71ff60bd2db9 (patch) | |
| tree | f83714cd404d31546c5cfffc7558720041ff4241 /include/hw/misc/iotkit-sysctl.h | |
| parent | 246dbeb76319fdaa7030403ea0273617331f6a44 (diff) | |
| download | focaccia-qemu-2672a6ca72311bdf97f9e324ab2e71ff60bd2db9.tar.gz focaccia-qemu-2672a6ca72311bdf97f9e324ab2e71ff60bd2db9.zip | |
hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register
The SSE-300 has a new PWRCTRL register at offset 0x1fc (previously reserved). This register controls accessibility of some registers in the Power Policy Units (PPUs). Since QEMU doesn't implement the PPUs, we don't need to implement any real behaviour for this register, so we just handle the UNLOCK bit which controls whether writes to the register itself are permitted and otherwise make it be reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-17-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/misc/iotkit-sysctl.h')
| -rw-r--r-- | include/hw/misc/iotkit-sysctl.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h index 980c2ddfd3..8859b15d73 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -53,6 +53,7 @@ struct IoTKitSysCtl { uint32_t initsvtor1; uint32_t nmi_enable; uint32_t ewctrl; + uint32_t pwrctrl; uint32_t pdcm_pd_sys_sense; uint32_t pdcm_pd_sram0_sense; uint32_t pdcm_pd_sram1_sense; |