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| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-08 15:51:51 +0100 |
|---|---|---|
| committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-02-21 22:24:58 +0000 |
| commit | 08944be1d91779aec4346cc569f87e4c915a944c (patch) | |
| tree | 20277a473f58dddcb433fd6e2f4f68027398b5ae /include/hw/misc/mips_cmgcr.h | |
| parent | 796b288f7be875045670f963ce99991b3c8e96ac (diff) | |
| download | focaccia-qemu-08944be1d91779aec4346cc569f87e4c915a944c.tar.gz focaccia-qemu-08944be1d91779aec4346cc569f87e4c915a944c.zip | |
hw/mips_cmgcr: allow GCR base to be moved
Support moving the GCR base address & updating the CPU's CP0 CMGCRBase register appropriately. This is required if a platform needs to move its GCRs away from other memory, as the MIPS Boston development board does to avoid its flash memory. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'include/hw/misc/mips_cmgcr.h')
| -rw-r--r-- | include/hw/misc/mips_cmgcr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h index a209d91ded..c9dfcb4b84 100644 --- a/include/hw/misc/mips_cmgcr.h +++ b/include/hw/misc/mips_cmgcr.h @@ -41,6 +41,9 @@ #define GCR_L2_CONFIG_BYPASS_SHF 20 #define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF) +/* GCR_BASE register fields */ +#define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL + /* GCR_GIC_BASE register fields */ #define GCR_GIC_BASE_GICEN_MSK 1 #define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL |