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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-02-23 09:59:40 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-02-23 09:59:40 +0000 |
| commit | 10f25e4844cb9b3f02fb032f88051dd5b65b4206 (patch) | |
| tree | 5bdce6b6ff69db978cf419e8b78975f7cd338bb3 /include/hw/misc/mips_cmgcr.h | |
| parent | e295a154c2a95f114e52ef4b0fb22b801b028bdc (diff) | |
| parent | d3473e147a754e999718bf6fcb015d9978c6a1ee (diff) | |
| download | focaccia-qemu-10f25e4844cb9b3f02fb032f88051dd5b65b4206.tar.gz focaccia-qemu-10f25e4844cb9b3f02fb032f88051dd5b65b4206.zip | |
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170222' into staging
MIPS patches 2017-02-22 Changes: * Add MIPS Boston board support # gpg: Signature made Wed 22 Feb 2017 00:08:00 GMT # gpg: using RSA key 0x2238EB86D5F797C2 # gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2 * remotes/yongbok/tags/mips-20170222: hw/mips: MIPS Boston board support hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller loader: Support Flattened Image Trees (FIT images) dtc: Update requirement to v1.4.2 target-mips: Provide function to test if a CPU supports an ISA hw/mips_gic: Update pin state on mask changes hw/mips_gictimer: provide API for retrieving frequency hw/mips_cmgcr: allow GCR base to be moved Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/misc/mips_cmgcr.h')
| -rw-r--r-- | include/hw/misc/mips_cmgcr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h index a209d91ded..c9dfcb4b84 100644 --- a/include/hw/misc/mips_cmgcr.h +++ b/include/hw/misc/mips_cmgcr.h @@ -41,6 +41,9 @@ #define GCR_L2_CONFIG_BYPASS_SHF 20 #define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF) +/* GCR_BASE register fields */ +#define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL + /* GCR_GIC_BASE register fields */ #define GCR_GIC_BASE_GICEN_MSK 1 #define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL |