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| author | Leon Alrae <leon.alrae@imgtec.com> | 2016-03-28 19:35:52 -0700 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-07-12 09:10:13 +0100 |
| commit | 19494f811a43c6bc226aa272d86300d9229224fe (patch) | |
| tree | 50d232e81783cb853b087fad2a3cd98495309818 /include/hw/misc/mips_cmgcr.h | |
| parent | e8bd336dd1af6d1073e9411bd1c47b045988b30a (diff) | |
| download | focaccia-qemu-19494f811a43c6bc226aa272d86300d9229224fe.tar.gz focaccia-qemu-19494f811a43c6bc226aa272d86300d9229224fe.zip | |
hw/mips/cps: create GIC block inside CPS
Add GIC to CPS and expose its interrupt pins instead of CPU's. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'include/hw/misc/mips_cmgcr.h')
| -rw-r--r-- | include/hw/misc/mips_cmgcr.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h index cc60eefa53..5b90e948b5 100644 --- a/include/hw/misc/mips_cmgcr.h +++ b/include/hw/misc/mips_cmgcr.h @@ -26,7 +26,9 @@ #define GCR_CONFIG_OFS 0x0000 #define GCR_BASE_OFS 0x0008 #define GCR_REV_OFS 0x0030 +#define GCR_GIC_BASE_OFS 0x0080 #define GCR_CPC_BASE_OFS 0x0088 +#define GCR_GIC_STATUS_OFS 0x00D0 #define GCR_CPC_STATUS_OFS 0x00F0 #define GCR_L2_CONFIG_OFS 0x0130 @@ -38,6 +40,11 @@ #define GCR_L2_CONFIG_BYPASS_SHF 20 #define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF) +/* GCR_GIC_BASE register fields */ +#define GCR_GIC_BASE_GICEN_MSK 1 +#define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL +#define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK) + /* GCR_CPC_BASE register fields */ #define GCR_CPC_BASE_CPCEN_MSK 1 #define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL @@ -52,8 +59,10 @@ struct MIPSGCRState { hwaddr gcr_base; MemoryRegion iomem; MemoryRegion *cpc_mr; + MemoryRegion *gic_mr; uint64_t cpc_base; + uint64_t gic_base; }; #endif /* _MIPS_GCR_H */ |