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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:20 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | a4b84608ba0eecce1d4858181457dc26582e6d28 (patch) | |
| tree | c657deeba29792d6cda5b76235810d8763cc2497 /include/hw/misc/sifive_u_prci.h | |
| parent | b609b7e3199912e16ef3b0447823f21fed73597e (diff) | |
| download | focaccia-qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.tar.gz focaccia-qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.zip | |
hw/riscv: Move sifive_test model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_test model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/misc/sifive_u_prci.h')
0 files changed, 0 insertions, 0 deletions