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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-09-22 18:23:14 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-09-22 18:23:14 +0100 |
| commit | e678c56f169bb576b607cda2a39c0b626ebfb221 (patch) | |
| tree | c22d8a7b3bba5280c0986efc892b8cebf9855f3d /include/hw/net/cadence_gem.h | |
| parent | 430da7a81d356e368ccd88dcca60f38da9aa5b9a (diff) | |
| parent | d675765a0244af1d65c292f2508009f1bd13e1b6 (diff) | |
| download | focaccia-qemu-e678c56f169bb576b607cda2a39c0b626ebfb221.tar.gz focaccia-qemu-e678c56f169bb576b607cda2a39c0b626ebfb221.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160922' into staging
target-arm queue: * add Cortex-A7 CPU * new ast2500 SoC model and evaluation board * palmetto-bmc: remove stray double assignment * aspeed: clean up RAM size handling * ptimer: framework for defining policy bits to change behaviour choices for different timer devices * ptimer: add some test cases * cadence_gem: add queue support * loader: support loading images to specified address spaces * loader: support auto-detect of ELF architecture from file * dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX * vmstateify ssd0323 * vmstateify ssi-sd * disas/arm.c: remove unused macros * imx: use 'const char', not 'char const' # gpg: Signature made Thu 22 Sep 2016 18:20:22 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160922: (36 commits) imx: Use 'const char', not 'char const' disas/arm.c: Remove unused macro definitions vmstateify ssi-sd vmstateify ssd0323 display dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX loader: Add AddressSpace loading support to targphys loader: Add AddressSpace loading support to uImages loader: Add AddressSpace loading support to ELFs loader: Allow a custom AddressSpace when loading ROMs loader: Use the specified MemoryRegion loader: Allow ELF loader to auto-detect the ELF arch xlnx-zynqmp: Set the number of priority queues cadence_gem: Correct indentation cadence_gem: Add queue support cadence_gem: Add support for screening cadence_gem: Add the num-priority-queues property cadence_gem: QOMify Cadence GEM tests: Add ptimer tests hw/ptimer: Suppress error messages under qtest hw/ptimer: Introduce timer policy feature ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/net/cadence_gem.h')
| -rw-r--r-- | include/hw/net/cadence_gem.h | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index f2e08e3575..c469ffe69b 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -30,7 +30,11 @@ #include "net/net.h" #include "hw/sysbus.h" -#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ +#define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ + +#define MAX_PRIORITY_QUEUES 8 +#define MAX_TYPE1_SCREENERS 16 +#define MAX_TYPE2_SCREENERS 16 typedef struct CadenceGEMState { /*< private >*/ @@ -40,7 +44,12 @@ typedef struct CadenceGEMState { MemoryRegion iomem; NICState *nic; NICConf conf; - qemu_irq irq; + qemu_irq irq[MAX_PRIORITY_QUEUES]; + + /* Static properties */ + uint8_t num_priority_queues; + uint8_t num_type1_screeners; + uint8_t num_type2_screeners; /* GEM registers backing store */ uint32_t regs[CADENCE_GEM_MAXREG]; @@ -59,12 +68,12 @@ typedef struct CadenceGEMState { uint8_t phy_loop; /* Are we in phy loopback? */ /* The current DMA descriptor pointers */ - uint32_t rx_desc_addr; - uint32_t tx_desc_addr; + uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES]; + uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES]; uint8_t can_rx_state; /* Debug only */ - unsigned rx_desc[2]; + unsigned rx_desc[MAX_PRIORITY_QUEUES][2]; bool sar_active[4]; } CadenceGEMState; |