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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2018-01-21 08:59:45 +0000 |
|---|---|---|
| committer | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2018-01-24 19:19:51 +0000 |
| commit | 9b30179460e5f6f8fc732a6c0e91f9d954310fe4 (patch) | |
| tree | 0f8a873b1166471a835b779a5019ab1b6325a6b0 /include/hw/pci-host/sabre.h | |
| parent | 5795162a9fb764ddf6ff8e62f9150a400d59f3f2 (diff) | |
| download | focaccia-qemu-9b30179460e5f6f8fc732a6c0e91f9d954310fe4.tar.gz focaccia-qemu-9b30179460e5f6f8fc732a6c0e91f9d954310fe4.zip | |
apb: rename apb.c to sabre.c
This is the final stage in correcting the naming convention with respect to sabre, APB and PBM. It is effectively a file rename from apb.c to sabre.c along with touching up a few constants to remove the remaining references to APB. Note that as part of the rename process the configuration variable CONFIG_PCI_APB is changed to CONFIG_PCI_SABRE. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
Diffstat (limited to 'include/hw/pci-host/sabre.h')
| -rw-r--r-- | include/hw/pci-host/sabre.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/include/hw/pci-host/sabre.h b/include/hw/pci-host/sabre.h new file mode 100644 index 0000000000..0f2ccc01c6 --- /dev/null +++ b/include/hw/pci-host/sabre.h @@ -0,0 +1,52 @@ +#ifndef PCI_HOST_APB_H +#define PCI_HOST_APB_H + +#include "hw/sparc/sun4u_iommu.h" + +#define MAX_IVEC 0x40 + +/* OBIO IVEC IRQs */ +#define OBIO_HDD_IRQ 0x20 +#define OBIO_NIC_IRQ 0x21 +#define OBIO_LPT_IRQ 0x22 +#define OBIO_FDD_IRQ 0x27 +#define OBIO_KBD_IRQ 0x29 +#define OBIO_MSE_IRQ 0x2a +#define OBIO_SER_IRQ 0x2b + +typedef struct SabrePCIState { + PCIDevice parent_obj; +} SabrePCIState; + +#define TYPE_SABRE_PCI_DEVICE "sabre-pci" +#define SABRE_PCI_DEVICE(obj) \ + OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE) + +typedef struct SabreState { + PCIHostState parent_obj; + + hwaddr special_base; + hwaddr mem_base; + MemoryRegion sabre_config; + MemoryRegion pci_config; + MemoryRegion pci_mmio; + MemoryRegion pci_ioport; + uint64_t pci_irq_in; + IOMMUState *iommu; + PCIBridge *bridgeA; + PCIBridge *bridgeB; + uint32_t pci_control[16]; + uint32_t pci_irq_map[8]; + uint32_t pci_err_irq_map[4]; + uint32_t obio_irq_map[32]; + qemu_irq ivec_irqs[MAX_IVEC]; + unsigned int irq_request; + uint32_t reset_control; + unsigned int nr_resets; +} SabreState; + +#define TYPE_SABRE "sabre" +#define SABRE_DEVICE(obj) \ + OBJECT_CHECK(SabreState, (obj), TYPE_SABRE) + +#endif |