diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2018-01-25 16:24:55 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-01-25 16:24:56 +0000 |
| commit | a3f9362af5c7071036fafb66665b85fda1e49bcc (patch) | |
| tree | bc66805eb2a71797d9146c1f8590f184bf24ff11 /include/hw/pci-host/sabre.h | |
| parent | b3bbe959b5dc3bf07041946455cc8e8d562bfd1f (diff) | |
| parent | 25c5d5acfbaa148b2da64b1f2c1401f87ebb0bb4 (diff) | |
| download | focaccia-qemu-a3f9362af5c7071036fafb66665b85fda1e49bcc.tar.gz focaccia-qemu-a3f9362af5c7071036fafb66665b85fda1e49bcc.zip | |
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging
qemu-sparc update # gpg: Signature made Thu 25 Jan 2018 13:44:58 GMT # gpg: using RSA key 0x5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: sun4u: implement power device sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events sabre: convert from SABRE_DPRINTF macro to trace-events apb: rename apb.c to sabre.c sun4u: rename apb variables and constants apb: rename QOM type from TYPE_APB to TYPE_SABRE apb: QOMify sabre PCI host bridge apb: change pbm_pci_host prefix functions to use sabre_pci prefix apb: rename APB functions to use sabre prefix simba: rename PBMPCIBridge and QOM types to reflect simba naming apb: split simba PCI bridge into hw/pci-bridge/simba.c sparc/leon3 irqmp: fix IRQ software ack Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/pci-host/sabre.h')
| -rw-r--r-- | include/hw/pci-host/sabre.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/include/hw/pci-host/sabre.h b/include/hw/pci-host/sabre.h new file mode 100644 index 0000000000..0f2ccc01c6 --- /dev/null +++ b/include/hw/pci-host/sabre.h @@ -0,0 +1,52 @@ +#ifndef PCI_HOST_APB_H +#define PCI_HOST_APB_H + +#include "hw/sparc/sun4u_iommu.h" + +#define MAX_IVEC 0x40 + +/* OBIO IVEC IRQs */ +#define OBIO_HDD_IRQ 0x20 +#define OBIO_NIC_IRQ 0x21 +#define OBIO_LPT_IRQ 0x22 +#define OBIO_FDD_IRQ 0x27 +#define OBIO_KBD_IRQ 0x29 +#define OBIO_MSE_IRQ 0x2a +#define OBIO_SER_IRQ 0x2b + +typedef struct SabrePCIState { + PCIDevice parent_obj; +} SabrePCIState; + +#define TYPE_SABRE_PCI_DEVICE "sabre-pci" +#define SABRE_PCI_DEVICE(obj) \ + OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE) + +typedef struct SabreState { + PCIHostState parent_obj; + + hwaddr special_base; + hwaddr mem_base; + MemoryRegion sabre_config; + MemoryRegion pci_config; + MemoryRegion pci_mmio; + MemoryRegion pci_ioport; + uint64_t pci_irq_in; + IOMMUState *iommu; + PCIBridge *bridgeA; + PCIBridge *bridgeB; + uint32_t pci_control[16]; + uint32_t pci_irq_map[8]; + uint32_t pci_err_irq_map[4]; + uint32_t obio_irq_map[32]; + qemu_irq ivec_irqs[MAX_IVEC]; + unsigned int irq_request; + uint32_t reset_control; + unsigned int nr_resets; +} SabreState; + +#define TYPE_SABRE "sabre" +#define SABRE_DEVICE(obj) \ + OBJECT_CHECK(SabreState, (obj), TYPE_SABRE) + +#endif |