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| author | Xiaojuan Yang <yangxiaojuan@loongson.cn> | 2022-07-29 15:30:18 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-07-29 15:07:55 -0700 |
| commit | 74725231d6fd1605d8b60c5afc2c0aec2f0b1e67 (patch) | |
| tree | d1d61e002dc917bdc59f8f48b230dc711228b002 /include/hw/pci-host | |
| parent | 587858ed0dd4833eadb3894d03d687fa461c6915 (diff) | |
| download | focaccia-qemu-74725231d6fd1605d8b60c5afc2c0aec2f0b1e67.tar.gz focaccia-qemu-74725231d6fd1605d8b60c5afc2c0aec2f0b1e67.zip | |
hw/loongarch: Change macro name 'LS7A_XXX' to 'VIRT_XXX'
Change macro name 'LS7A_XXX' to 'VIRT_XXX', as the loongarch virt machinue use the GPEX bridge instead of LS7A bridge. So the macro name should keep consistency. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220729073018.27037-3-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/hw/pci-host')
| -rw-r--r-- | include/hw/pci-host/ls7a.h | 43 |
1 files changed, 20 insertions, 23 deletions
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index 0fdc86b973..cdde0af1f8 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -15,34 +15,31 @@ #include "qemu/range.h" #include "qom/object.h" -#define LS7A_PCI_MEM_BASE 0x40000000UL -#define LS7A_PCI_MEM_SIZE 0x40000000UL -#define LS7A_PCI_IO_OFFSET 0x4000 -#define LS_PCIECFG_BASE 0x20000000 -#define LS_PCIECFG_SIZE 0x08000000 -#define LS7A_PCI_IO_BASE 0x18004000UL -#define LS7A_PCI_IO_SIZE 0xC000 +#define VIRT_PCI_MEM_BASE 0x40000000UL +#define VIRT_PCI_MEM_SIZE 0x40000000UL +#define VIRT_PCI_IO_OFFSET 0x4000 +#define VIRT_PCI_CFG_BASE 0x20000000 +#define VIRT_PCI_CFG_SIZE 0x08000000 +#define VIRT_PCI_IO_BASE 0x18004000UL +#define VIRT_PCI_IO_SIZE 0xC000 -#define LS7A_PCI_MEM_BASE 0x40000000UL -#define LS7A_PCI_MEM_SIZE 0x40000000UL - -#define LS7A_PCH_REG_BASE 0x10000000UL -#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE) -#define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL +#define VIRT_PCH_REG_BASE 0x10000000UL +#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE) +#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL /* * According to the kernel pch irq start from 64 offset * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs * used for pci device. */ -#define PCH_PIC_IRQ_OFFSET 64 -#define LS7A_DEVICE_IRQS 16 -#define LS7A_PCI_IRQS 48 -#define LS7A_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) -#define LS7A_UART_BASE 0x1fe001e0 -#define LS7A_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3) -#define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000) -#define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100) -#define LS7A_RTC_LEN 0x100 -#define LS7A_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4) +#define PCH_PIC_IRQ_OFFSET 64 +#define VIRT_DEVICE_IRQS 16 +#define VIRT_PCI_IRQS 48 +#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) +#define VIRT_UART_BASE 0x1fe001e0 +#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3) +#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000) +#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100) +#define VIRT_RTC_LEN 0x100 +#define VIRT_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4) #endif |