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| author | Cédric Le Goater <clg@kaod.org> | 2019-03-07 23:35:44 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-03-12 14:33:04 +1100 |
| commit | 5dad902ce09877a97a6f32e5f6c75b4f8506bd73 (patch) | |
| tree | e17c6171757a39c2072a4b3909b9c77dbf5150ac /include/hw/ppc/pnv_core.h | |
| parent | 90ef386c74b1b2c485b69a1bdb24895bebd45502 (diff) | |
| download | focaccia-qemu-5dad902ce09877a97a6f32e5f6c75b4f8506bd73.tar.gz focaccia-qemu-5dad902ce09877a97a6f32e5f6c75b4f8506bd73.zip | |
ppc/pnv: POWER9 XSCOM quad support
The POWER9 processor does not support per-core frequency control. The cores are arranged in groups of four, along with their respective L2 and L3 caches, into a structure known as a Quad. The frequency must be managed at the Quad level. Provide a basic Quad model to fake the settings done by the firmware on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special BAR setting for the TIMA area of XIVE because it resides on the same address on all chips. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-12-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw/ppc/pnv_core.h')
| -rw-r--r-- | include/hw/ppc/pnv_core.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index cbe9ad36f3..50cdb2b358 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -58,4 +58,14 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu) return (PnvCPUState *)cpu->machine_data; } +#define TYPE_PNV_QUAD "powernv-cpu-quad" +#define PNV_QUAD(obj) \ + OBJECT_CHECK(PnvQuad, (obj), TYPE_PNV_QUAD) + +typedef struct PnvQuad { + DeviceState parent_obj; + + uint32_t id; + MemoryRegion xscom_regs; +} PnvQuad; #endif /* _PPC_PNV_CORE_H */ |