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| author | Cédric Le Goater <clg@fr.ibm.com> | 2016-04-03 19:57:50 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-04-05 10:38:24 +1000 |
| commit | 5c94b2a5e5ef7f91270ce034d2095c6ed924c61d (patch) | |
| tree | 603be713f964f3c0ccc3db5e3b47419ee8dafaa2 /include/hw/ppc/spapr.h | |
| parent | 2e3a76ae3e47d502f9f0c4424b719945fba9d459 (diff) | |
| download | focaccia-qemu-5c94b2a5e5ef7f91270ce034d2095c6ed924c61d.tar.gz focaccia-qemu-5c94b2a5e5ef7f91270ce034d2095c6ed924c61d.zip | |
ppc: Rework POWER7 & POWER8 exception model
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This patch fixes the current AIL implementation for POWER8. The
interrupt vector address can be calculated directly from LPCR when the
exception is handled. The excp_prefix update becomes useless and we
can cleanup the H_SET_MODE hcall.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: Removed LPES0/1 handling for HV vs. !HV
Fixed LPCR_ILE case for POWERPC_EXCP_POWER8 ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
[dwg: This was written as a cleanup, but it also fixes a real bug
where setting an alternative interrupt location would not be
correctly migrated]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw/ppc/spapr.h')
| -rw-r--r-- | include/hw/ppc/spapr.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 098d85d1a1..815d5eec45 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -204,11 +204,6 @@ struct sPAPRMachineState { #define H_SET_MODE_ENDIAN_BIG 0 #define H_SET_MODE_ENDIAN_LITTLE 1 -/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ -#define H_SET_MODE_ADDR_TRANS_NONE 0 -#define H_SET_MODE_ADDR_TRANS_0001_8000 2 -#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 - /* VASI States */ #define H_VASI_INVALID 0 #define H_VASI_ENABLED 1 |