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| author | Shivaprasad G Bhat <sbhat@linux.ibm.com> | 2025-01-17 04:07:01 +0000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2025-03-11 22:43:32 +1000 |
| commit | 5f361ea187ba5f876757d4c90952ff23810f24f5 (patch) | |
| tree | 194f59783b99356ec12c1f1dd78097a88b13dfaa /include/hw/ppc/spapr.h | |
| parent | 7ea6e125297050a239b4028cae5ea3ffbc374861 (diff) | |
| download | focaccia-qemu-5f361ea187ba5f876757d4c90952ff23810f24f5.tar.gz focaccia-qemu-5f361ea187ba5f876757d4c90952ff23810f24f5.zip | |
ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine
As per the PAPR, bit 0 of byte 64 in pa-features property indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find whether kvm supports 2nd DAWR or not. If it's supported, allow user to set the pa-feature bit in guest DT using cap-dawr1 machine capability. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Message-ID: <173708681866.1678.11128625982438367069.stgit@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'include/hw/ppc/spapr.h')
| -rw-r--r-- | include/hw/ppc/spapr.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index a6c0547e31..d227f0b94b 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -83,8 +83,10 @@ typedef enum { #define SPAPR_CAP_AIL_MODE_3 0x0C /* Nested PAPR */ #define SPAPR_CAP_NESTED_PAPR 0x0D +/* DAWR1 */ +#define SPAPR_CAP_DAWR1 0x0E /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_PAPR + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_DAWR1 + 1) /* * Capability Values @@ -406,6 +408,7 @@ struct SpaprMachineState { #define H_SET_MODE_RESOURCE_SET_DAWR0 2 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 #define H_SET_MODE_RESOURCE_LE 4 +#define H_SET_MODE_RESOURCE_SET_DAWR1 5 /* Flags for H_SET_MODE_RESOURCE_LE */ #define H_SET_MODE_ENDIAN_BIG 0 @@ -1003,6 +1006,7 @@ extern const VMStateDescription vmstate_spapr_cap_fwnmi; extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; extern const VMStateDescription vmstate_spapr_cap_ail_mode_3; extern const VMStateDescription vmstate_spapr_wdt; +extern const VMStateDescription vmstate_spapr_cap_dawr1; static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) { |