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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-04-11 17:29:59 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-04-26 12:41:55 +1000 |
| commit | 4d1df88b63c68f84a3c1a84a7f88cb8e6fa99490 (patch) | |
| tree | df8f3cc20ec8a2c29ab9b5ffed551f1887104acc /include/hw/ppc | |
| parent | 71cd4dace9abf51469cfbf6db622124993955f78 (diff) | |
| download | focaccia-qemu-4d1df88b63c68f84a3c1a84a7f88cb8e6fa99490.tar.gz focaccia-qemu-4d1df88b63c68f84a3c1a84a7f88cb8e6fa99490.zip | |
ppc/pnv: Add support for POWER8+ LPC Controller
It adds the Naples chip which supports proper LPC interrupts via the
LPC controller rather than via an external CPLD.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: - updated for qemu-2.9
- ported on latest PowerNV patchset
- moved the IRQ handler in pnv_lpc.c
- introduced pnv_lpc_isa_irq_create() to create the ISA IRQs ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw/ppc')
| -rw-r--r-- | include/hw/ppc/pnv_lpc.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 38e5506975..ccf969af94 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -23,6 +23,8 @@ #define PNV_LPC(obj) \ OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) +typedef struct PnvPsi PnvPsi; + typedef struct PnvLpcController { DeviceState parent; @@ -62,6 +64,12 @@ typedef struct PnvLpcController { /* XSCOM registers */ MemoryRegion xscom_regs; + + /* PSI to generate interrupts */ + PnvPsi *psi; } PnvLpcController; +qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, + int nirqs); + #endif /* _PPC_PNV_LPC_H */ |