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| author | Nicholas Piggin <npiggin@gmail.com> | 2024-05-26 21:24:00 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-07-26 09:21:06 +1000 |
| commit | 60d30cff8472c0bf05a40b0f55221fb4efb768e2 (patch) | |
| tree | 5f88c3fc969ee90d98d9be9104af4af6344aa928 /include/hw/ppc | |
| parent | 0ca94b2f11223d41258e6a7a046e5ccde831de46 (diff) | |
| download | focaccia-qemu-60d30cff8472c0bf05a40b0f55221fb4efb768e2.tar.gz focaccia-qemu-60d30cff8472c0bf05a40b0f55221fb4efb768e2.zip | |
target/ppc: Move SPR indirect registers into PnvCore
SPRC/SPRD were recently added to all BookS CPUs supported, but they are only tested on POWER9 and POWER10, so restrict them to those CPUs. SPR indirect scratch registers presently replicated per-CPU like SMT SPRs, but the PnvCore is a better place for them since they are restricted to P9/P10. Also add SPR indirect read access to core thread state for POWER9 since skiboot accesses that when booting to check for big-core mode. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'include/hw/ppc')
| -rw-r--r-- | include/hw/ppc/pnv_core.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index ffec8516ae..693acb189b 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -53,6 +53,7 @@ struct PnvCore { uint32_t hwid; uint64_t hrmor; + target_ulong scratch[8]; /* SPRC/SPRD indirect SCRATCH registers */ PnvCoreTODState tod_state; PnvChip *chip; |