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| author | Bin Meng <bin.meng@windriver.com> | 2020-10-28 13:30:03 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 07:17:23 -0800 |
| commit | 933f73f13e5ceb9357e9c9d51ce39c43aa1d534f (patch) | |
| tree | 1276d3fe98992197dd292cca037981e77fe6c78a /include/hw/riscv/microchip_pfsoc.h | |
| parent | 3400b15bbe0fbc672fee9a18268154b07a1fed2e (diff) | |
| download | focaccia-qemu-933f73f13e5ceb9357e9c9d51ce39c43aa1d534f.tar.gz focaccia-qemu-933f73f13e5ceb9357e9c9d51ce39c43aa1d534f.zip | |
hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv/microchip_pfsoc.h')
| -rw-r--r-- | include/hw/riscv/microchip_pfsoc.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 8bfc7e1a85..5b81e26241 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -24,6 +24,7 @@ #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/sifive_pdma.h" +#include "hw/misc/mchp_pfsoc_dmc.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" @@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState { RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; + MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; + MchpPfSoCDdrCfgState ddr_cfg; MchpPfSoCMMUartState *serial0; MchpPfSoCMMUartState *serial1; MchpPfSoCMMUartState *serial2; @@ -82,7 +85,9 @@ enum { MICROCHIP_PFSOC_MMUART0, MICROCHIP_PFSOC_SYSREG, MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_DDR_SGMII_PHY, MICROCHIP_PFSOC_EMMC_SD, + MICROCHIP_PFSOC_DDR_CFG, MICROCHIP_PFSOC_MMUART1, MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, |