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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-10-18 12:38:39 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-10-22 23:35:47 +1000 |
| commit | ef6310064820183cce7c5969cae293e680c57679 (patch) | |
| tree | b5ffff1909b00321badc12c0f31d987d1aa70a6f /include/hw/riscv/opentitan.h | |
| parent | b550f89457ef5022231f8255ae1a6ba496c492b1 (diff) | |
| download | focaccia-qemu-ef6310064820183cce7c5969cae293e680c57679.tar.gz focaccia-qemu-ef6310064820183cce7c5969cae293e680c57679.zip | |
hw/riscv: opentitan: Update to the latest build
Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
Diffstat (limited to 'include/hw/riscv/opentitan.h')
| -rw-r--r-- | include/hw/riscv/opentitan.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 9f93bebdac..eac35ef590 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -20,7 +20,7 @@ #define HW_OPENTITAN_H #include "hw/riscv/riscv_hart.h" -#include "hw/intc/ibex_plic.h" +#include "hw/intc/sifive_plic.h" #include "hw/char/ibex_uart.h" #include "hw/timer/ibex_timer.h" #include "qom/object.h" @@ -34,7 +34,7 @@ struct LowRISCIbexSoCState { /*< public >*/ RISCVHartArrayState cpus; - IbexPlicState plic; + SiFivePLICState plic; IbexUartState uart; IbexTimerState timer; @@ -87,7 +87,7 @@ enum { }; enum { - IBEX_TIMER_TIMEREXPIRED0_0 = 125, + IBEX_TIMER_TIMEREXPIRED0_0 = 126, IBEX_UART0_RX_PARITY_ERR_IRQ = 8, IBEX_UART0_RX_TIMEOUT_IRQ = 7, IBEX_UART0_RX_BREAK_ERR_IRQ = 6, |