diff options
| author | Tommy Wu <tommy.wu@sifive.com> | 2025-01-06 13:43:33 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:34 +1000 |
| commit | c1149f69ab711bf6ccdc1da492f5be47f1ebf67e (patch) | |
| tree | d0bad2eca9da78b465c022ae81ea797de09bde51 /include/hw/riscv/riscv_hart.h | |
| parent | 5db557f82bff480437275d4cc9e0b5463bc04484 (diff) | |
| download | focaccia-qemu-c1149f69ab711bf6ccdc1da492f5be47f1ebf67e.tar.gz focaccia-qemu-c1149f69ab711bf6ccdc1da492f5be47f1ebf67e.zip | |
target/riscv: Handle Smrnmi interrupt and exception
Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to handle the RNMI signals. Signed-off-by: Frank Chang <frank.chang@sifive.com> Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250106054336.1878291-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv/riscv_hart.h')
| -rw-r--r-- | include/hw/riscv/riscv_hart.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 912b4a2682..a6ed73a195 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -38,6 +38,10 @@ struct RISCVHartArrayState { uint32_t hartid_base; char *cpu_type; uint64_t resetvec; + uint32_t num_rnmi_irqvec; + uint64_t *rnmi_irqvec; + uint32_t num_rnmi_excpvec; + uint64_t *rnmi_excpvec; RISCVCPU *harts; }; |