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authorAlistair Francis <alistair.francis@wdc.com>2020-05-13 10:42:46 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-06-19 08:24:07 -0700
commit5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1 (patch)
treecf6ea7f11f5f0aafdc450287a2e4cbfc14acc1aa /include/hw/riscv/sifive_e.h
parent354908cee1f7ff761b5fedbdb6376c378c10f941 (diff)
downloadfocaccia-qemu-5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1.tar.gz
focaccia-qemu-5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1.zip
sifive_e: Support the revB machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv/sifive_e.h')
-rw-r--r--include/hw/riscv/sifive_e.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index d386ea9223..637414130b 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -45,6 +45,7 @@ typedef struct SiFiveEState {
 
     /*< public >*/
     SiFiveESoCState soc;
+    bool revb;
 } SiFiveEState;
 
 #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")