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| author | Michael Clark <mjc@sifive.com> | 2018-03-04 13:27:37 +1300 |
|---|---|---|
| committer | Michael Clark <mjc@sifive.com> | 2018-05-06 10:39:38 +1200 |
| commit | 42b3a4b7ccbbf419df926939b273fe3b8a6dca1f (patch) | |
| tree | 30151c785ec50bea8038d92dda9d85930a934474 /include/hw/riscv/virt.h | |
| parent | b7938980fbd3209fd94b17c98c54ec044b762417 (diff) | |
| download | focaccia-qemu-42b3a4b7ccbbf419df926939b273fe3b8a6dca1f.tar.gz focaccia-qemu-42b3a4b7ccbbf419df926939b273fe3b8a6dca1f.zip | |
RISC-V: Remove unused class definitions
Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv/virt.h')
| -rw-r--r-- | include/hw/riscv/virt.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 655e85ddbd..b91a4125dd 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,10 +19,6 @@ #ifndef HW_VIRT_H #define HW_VIRT_H -#define TYPE_RISCV_VIRT_BOARD "riscv.virt" -#define VIRT(obj) \ - OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) - typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -45,7 +41,6 @@ enum { VIRT_DRAM }; - enum { UART0_IRQ = 10, VIRTIO_IRQ = 1, /* 1 to 8 */ |