diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2020-05-13 10:37:08 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-03 09:11:51 -0700 |
| commit | 0869490b1cc4d917ac4eb3a02cac7d71149def91 (patch) | |
| tree | b0ee6cbea827562c00d57835ef1b34774e5ea9db /include/hw/riscv | |
| parent | f33559a427134ff1ae49982bdca8d10f81837204 (diff) | |
| download | focaccia-qemu-0869490b1cc4d917ac4eb3a02cac7d71149def91.tar.gz focaccia-qemu-0869490b1cc4d917ac4eb3a02cac7d71149def91.zip | |
riscv: sifive_e: Manually define the machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/sifive_e.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 25ce7aa9d5..414992119e 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -47,6 +47,10 @@ typedef struct SiFiveEState { SiFiveESoCState soc; } SiFiveEState; +#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e") +#define RISCV_E_MACHINE(obj) \ + OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE) + enum { SIFIVE_E_DEBUG, SIFIVE_E_MROM, |