hw/riscv: Move sifive_gpio model to hw/gpio

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.

Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supported trace target in that directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

3 files changed, 2 insertions, 78 deletions

diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 637414130b..b1400843c2 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -21,7 +21,7 @@
 
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 
 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
 #define RISCV_E_SOC(obj) \
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
deleted file mode 100644
index cf12fcfd62..0000000000
--- a/include/hw/riscv/sifive_gpio.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * SiFive System-on-Chip general purpose input/output register definition
- *
- * Copyright 2019 AdaCore
- *
- * Base on nrf51_gpio.c:
- *
- * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
- *
- * This code is licensed under the GPL version 2 or later.  See
- * the COPYING file in the top-level directory.
- */
-
-#ifndef SIFIVE_GPIO_H
-#define SIFIVE_GPIO_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
-#define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
-
-#define SIFIVE_GPIO_PINS 32
-
-#define SIFIVE_GPIO_SIZE 0x100
-
-#define SIFIVE_GPIO_REG_VALUE      0x000
-#define SIFIVE_GPIO_REG_INPUT_EN   0x004
-#define SIFIVE_GPIO_REG_OUTPUT_EN  0x008
-#define SIFIVE_GPIO_REG_PORT       0x00C
-#define SIFIVE_GPIO_REG_PUE        0x010
-#define SIFIVE_GPIO_REG_DS         0x014
-#define SIFIVE_GPIO_REG_RISE_IE    0x018
-#define SIFIVE_GPIO_REG_RISE_IP    0x01C
-#define SIFIVE_GPIO_REG_FALL_IE    0x020
-#define SIFIVE_GPIO_REG_FALL_IP    0x024
-#define SIFIVE_GPIO_REG_HIGH_IE    0x028
-#define SIFIVE_GPIO_REG_HIGH_IP    0x02C
-#define SIFIVE_GPIO_REG_LOW_IE     0x030
-#define SIFIVE_GPIO_REG_LOW_IP     0x034
-#define SIFIVE_GPIO_REG_IOF_EN     0x038
-#define SIFIVE_GPIO_REG_IOF_SEL    0x03C
-#define SIFIVE_GPIO_REG_OUT_XOR    0x040
-
-typedef struct SIFIVEGPIOState {
-    SysBusDevice parent_obj;
-
-    MemoryRegion mmio;
-
-    qemu_irq irq[SIFIVE_GPIO_PINS];
-    qemu_irq output[SIFIVE_GPIO_PINS];
-
-    uint32_t value;             /* Actual value of the pin */
-    uint32_t input_en;
-    uint32_t output_en;
-    uint32_t port;              /* Pin value requested by the user */
-    uint32_t pue;
-    uint32_t ds;
-    uint32_t rise_ie;
-    uint32_t rise_ip;
-    uint32_t fall_ie;
-    uint32_t fall_ip;
-    uint32_t high_ie;
-    uint32_t high_ip;
-    uint32_t low_ie;
-    uint32_t low_ip;
-    uint32_t iof_en;
-    uint32_t iof_sel;
-    uint32_t out_xor;
-    uint32_t in;
-    uint32_t in_mask;
-
-    /* config */
-    uint32_t ngpio;
-} SIFIVEGPIOState;
-
-#endif /* SIFIVE_GPIO_H */
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 936a3bd0b1..fe5c580845 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -23,7 +23,7 @@
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 #include "hw/misc/sifive_u_otp.h"
 #include "hw/misc/sifive_u_prci.h"