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| author | Jim Shu <jim.shu@sifive.com> | 2024-11-20 23:39:33 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-12-20 11:22:47 +1000 |
| commit | b4132a9e62978e247bce66e70499c4e2cad8d870 (patch) | |
| tree | a9efc023a17630dd15c0b9de7067cfc321c39597 /include/hw/riscv | |
| parent | d2ed9fffba07a7ce87f33d5b9662e3e8eadb11d4 (diff) | |
| download | focaccia-qemu-b4132a9e62978e247bce66e70499c4e2cad8d870.tar.gz focaccia-qemu-b4132a9e62978e247bce66e70499c4e2cad8d870.zip | |
hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20241120153935.24706-2-jim.shu@sifive.com> [ Changes by AF - Store fdt_load_addr_hi32 in the reset vector ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/boot.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f778b560de..34a80c5ff4 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -49,7 +49,7 @@ target_ulong riscv_load_kernel(MachineState *machine, bool load_initrd, symbol_fn_t sym_cb); uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, - MachineState *ms); + MachineState *ms, RISCVHartArrayState *harts); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, |