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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-04-23 18:40:57 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-19 08:24:07 -0700 |
| commit | b9fc51354cdc8e2623925c8fd76d7634240a28af (patch) | |
| tree | 3b93c71c023bf147010c5201ba43b8d2507e661c /include/hw/riscv | |
| parent | 879f60f01c1c655676207ea73d9250a7bc4a915f (diff) | |
| download | focaccia-qemu-b9fc51354cdc8e2623925c8fd76d7634240a28af.tar.gz focaccia-qemu-b9fc51354cdc8e2623925c8fd76d7634240a28af.zip | |
riscv/opentitan: Connect the PLIC device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/opentitan.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index a4b6499444..76f72905a8 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -20,6 +20,7 @@ #define HW_OPENTITAN_H #include "hw/riscv/riscv_hart.h" +#include "hw/intc/ibex_plic.h" #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" #define RISCV_IBEX_SOC(obj) \ @@ -31,6 +32,8 @@ typedef struct LowRISCIbexSoCState { /*< public >*/ RISCVHartArrayState cpus; + IbexPlicState plic; + MemoryRegion flash_mem; MemoryRegion rom; } LowRISCIbexSoCState; |