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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2025-07-11 21:46:36 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-07-15 00:25:21 +0200 |
| commit | 6f8ce26bb00db66e6cec632f16df3cd13e4df934 (patch) | |
| tree | 7e91c12e348987038849220c7bf90a8d14dc974e /include/hw/scsi/esp.h | |
| parent | ab1207401edc19d17fad6cb473cd6beae31b1dd1 (diff) | |
| download | focaccia-qemu-6f8ce26bb00db66e6cec632f16df3cd13e4df934.tar.gz focaccia-qemu-6f8ce26bb00db66e6cec632f16df3cd13e4df934.zip | |
esp.c: only allow ESP commands permitted in the current asc_mode
If an ESP command is issued in an incorrect mode then an illegal command
interrupt should be generated. Add a new esp_cmd_is_valid() function to
indicate whether the ESP command is valid for the current mode, and if not
then raise the illegal command interrupt.
This fixes WinNT MIPS which issues ICCS after a Chip Reset which is not
permitted, but will fail with an INACCESSIBLE_BOOT_DEVICE error unless an
interrupt is generated.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Fixes: 83428f7a97 ("esp.c: move write_response() non-DMA logic to esp_do_nodma()")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2464
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250711204636.542964-8-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'include/hw/scsi/esp.h')
| -rw-r--r-- | include/hw/scsi/esp.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 6327060c7c..3526bad746 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -111,6 +111,13 @@ struct SysBusESPState { #define CMD_DMA 0x80 #define CMD_CMD 0x7f +#define CMD_GRP_MASK 0x70 + +#define CMD_GRP_MISC 0x00 +#define CMD_GRP_INIT 0x01 +#define CMD_GRP_TRGT 0x02 +#define CMD_GRP_DISC 0x04 + #define CMD_NOP 0x00 #define CMD_FLUSH 0x01 #define CMD_RESET 0x02 @@ -145,6 +152,7 @@ struct SysBusESPState { #define INTR_FC 0x08 #define INTR_BS 0x10 #define INTR_DC 0x20 +#define INTR_IL 0x40 #define INTR_RST 0x80 #define SEQ_0 0x0 |