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authorBernhard Beschow <shentey@gmail.com>2023-10-07 14:38:12 +0200
committerMichael S. Tsirkin <mst@redhat.com>2023-10-22 05:18:16 -0400
commit32f29b26ff150dba6d1c455b826e44447b9ead45 (patch)
treeff3ce031c9ebb08b54175664e031f8f062b079f6 /include/hw/southbridge/piix.h
parent8b6cf5128ee510729895e00a669fa7ce7457c949 (diff)
downloadfocaccia-qemu-32f29b26ff150dba6d1c455b826e44447b9ead45.tar.gz
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hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-5-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/southbridge/piix.h')
-rw-r--r--include/hw/southbridge/piix.h5
1 files changed, 2 insertions, 3 deletions
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 278171752f..2317bb7974 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -27,7 +27,6 @@
  */
 #define PIIX_RCR_IOPORT 0xcf9
 
-#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
 
 struct PIIXState {
@@ -39,10 +38,10 @@ struct PIIXState {
      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
      *
      * PIRQ is mapped to PIC pins, we track it by
-     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+     * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
      * pic_irq * PIIX_NUM_PIRQS + pirq
      */
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
 #error "unable to encode pic state in 64bit in pic_levels."
 #endif
     uint64_t pic_levels;