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| author | Philippe Mathieu-Daudé <philmd@redhat.com> | 2019-10-15 14:05:42 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@redhat.com> | 2019-11-05 23:33:12 +0100 |
| commit | 4b19de14b145ac1df3082f625e3b8f9dcb0e1918 (patch) | |
| tree | 5d689de0bc7383e0b03da4b0bd5d04c7921a12d0 /include/hw/southbridge/piix.h | |
| parent | 0063454affb3c5a595539a3cad9e20e7229d8fac (diff) | |
| download | focaccia-qemu-4b19de14b145ac1df3082f625e3b8f9dcb0e1918.tar.gz focaccia-qemu-4b19de14b145ac1df3082f625e3b8f9dcb0e1918.zip | |
hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
The IRQ Route Control registers definitions belong to the PIIX chipset. We were only defining the 'A' register. Define the other B, C and D registers, and use them. Acked-by: Paul Durrant <paul@xen.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Diffstat (limited to 'include/hw/southbridge/piix.h')
| -rw-r--r-- | include/hw/southbridge/piix.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index e49d4a6bbe..094508b928 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); +/* PIRQRC[A:D]: PIRQx Route Control Registers */ +#define PIIX_PIRQCA 0x60 +#define PIIX_PIRQCB 0x61 +#define PIIX_PIRQCC 0x62 +#define PIIX_PIRQCD 0x63 + /* * Reset Control Register: PCI-accessible ISA-Compatible Register at address * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). |